A latch is a fundamental digital logic circuit of numerous logic devices such as microcontrollers, processors, field programmable gate arrays (FPGAs) and many others. In general, the latch is an electronic circuit that has two stable states and therefore can store one bit of information. Its output depends on both current and previous inputs. Such a circuit is described as a sequential logic. There are several designs of latch circuits such as SR-latch, JK-latch, D-latch, T-latch, etc. These circuits are mostly built using a complimentary metal-oxide-semiconductor (CMOS) technology employing complementary and symmetrical pairs of p-type and n-type of metal-oxide-semiconductor field effect transistors (MOSFETs) for logic functions. A CMOS inverter is one of key elements of the latches. The conventional CMOS inverter is volatile.
FIG. 1 shows a nonvolatile CMOS inverter 10 according to a prior art. The inverter 10 includes an p-type MOS (pMOS) transistor 1P1, an n-type MOS (nMOS) transistor 1N1, and a nonvolatile magnetoresitive (MR) memory element (or magnetic tunnel junction (MTJ)) 1J1. Gates of the pMOS transistor 1P1 and the nMOS transistor 1N1 are connected in common to serve as an input terminal IN. Drains of the transistors 1P1 and 1N1 also connected in common serve as an output terminal OUT. Sources of the pMOS transistor 1P1 and the nMOS transistor 1N1 are connected to voltage sources VDD and VSS, respectively. The nonvolatile memory element 1J1 is connected to the output terminal OUT of the inverter 10 at its first end and to a memory (intermediate) voltage source VM at its second end, where VDD>VM>VSS. The source terminal of the nMOS transistor 1N1 can be connected to a grounding source GRD (VDD>VM>GRD). Moreover, the MTJ element 1J1 can also be connected to the grounding source GRD. In this case the following relation between electric potentials of the voltage sources can be observed: VDD>GRD>VSS.
The MR element 1J1 can comprise at least a free (or storage) layer 12 with a reversible magnetization direction (shown by a dashed arrow), a pinned (or reference) layer 14 with a fixed magnetization direction (shown by a solid arrow), and a nonmagnetic insulating tunnel barrier layer 16 sandwiched in-between. Resistance of the memory element 1J1 depends on a mutual orientation of the magnetization directions in the free 12 and pinned 14 layers. The resistance has a highest value (logic “1”) when the magnetization directions are antiparallel to each other, and the lowest value (logic “0”) when they are parallel. Hence the magnetization direction of the free layer 12 can have two stable logic states. It can be controlled by a direction of a spin-polarized current IS running through the element 1J1 in a direction perpendicular to layers surface (or plane). The direction of the current IS and hence the magnetization direction of the free layer 12 depends of the polarity of the input signal at the gates of the transistors 1P1 and 1N1.
When an input signal IN=1 (logic “1”) is applied to the common gate terminal of the transistors 1P1 and 1N1, the pMOS transistor 1P1 is “Off” and the nMOS transistor 1N1 is “On”. The spin-polarized current IS is running in the direction from the memory source VM to the source VSS. The current IS of this direction can force the magnetization direction of the free layer 12 in parallel to the magnetization direction of the pinned layer 14, which corresponds to a logic “0”. When the input signal is changed to IN=0 (a logic “0”), the pMOS transistor 1P1 turns “On” but the nMOS transistor 1N1 is “Off”. The spin-polarizing current IS is running in the opposite direction from the logic source VDD to the memory source VM. As a result, the magnetization direction of the free layer 12 can be forced in antiparallel to the magnetization direction of the pinned layer 14. This mutual orientation of the magnetizations corresponds to a high resistance state or to logic “1”. Hence, the logic value of the memory element 1J1 corresponds to a logic value at the output terminal of the conventional volatile CMOS inverter. The memory element 1J1 can provide a nonvolatile storage of the logic state of the inverter 10. The data may not be lost when the power is off.
CMOS-based latches are volatile. They can lose their data when the power is off. The present disclosure addresses to this problem.